1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to an interface circuit including a level-down shifter.
2. Discussion of the Related Art
For semiconductor devices used in mobile products, low power consumption is an important characteristic. In general, semiconductor integrated circuits (ICs) require an external power source to provide power to operate. Typically, the external power source is pulled down to an internal power and the internal power is used to operate the IC or chip. For example, semiconductor ICs receive an external power of about 3.3V and generate an internal power of about 1.8V to about 2.2V. An interface circuit is needed to handle a voltage difference between a circuit operating at 3.3V and a circuit operating at 1.8V. The interface circuit is generally used in an input buffer circuit or an output buffer circuit that is interfaced with the outside.
FIG. 1 shows signal transmission between a first circuit 110 operating at an external power of about 3.3V and a second circuit 120 operating at an internal power of about 1.8V. An input signal IN that undergoes full swing from 0V to 3.3V is input to the first circuit 110. For convenience of explanation, it is understood that the first circuit 110 and the second circuit 120 perform simple inverting operation. The first circuit 110 inverts the input signal IN and outputs the inverted IN signal to a first node NA and the second circuit 120 in turn inverts the inverting signal at NA and outputs the resulting signal to a second node NB.
Here, referring to a signal waveform of the first node NA and a signal waveform of the second node NB, the first node NA transits from a logic high level to a logic low level by swinging from about 3.3V to 0V and transits from a logic low level to a logic high level by swinging from 0V to about 3.3V. Thus, a midpoint of the transition of the first node NA is approximately about 1.65V. Since the operating power of the second circuit 120 is about 1.8V, a trigger point T1 of the second circuit 120 is lowered below a midpoint of the trigger point of the first circuit 110, i.e., at about 1.65V.
In response to the first node NA that transits from the logic high level of about 3.3V to the logic low level of 0V, the second node NB transits from the logic low level of 0V to the logic high level of about 1.8V. Since a trigger point of the second circuit 120 is low, the amount of time required for the transition of the signal at the second node NB increases. In response to the first node NA that transits from the logic low level of 0V to the logic high level of about 3.3V, the second node NB transits from the logic high level of 1.8V to the logic low level of 0V and the amount of time required for the transition of the second node NB decreases. As a result, there exists a transition interval Δ between the midpoint of the transition from the logic low level to the logic high level and the midpoint of the transition from the logic high level to the logic low level. Such a transition interval causes skew. Moreover, occurrence of skew increases as the difference between the external power sources increases. Also, occurrence of skew changes the duty cycle of a signal at the second node NB.
Furthermore, the change in the duty cycle of the signal increases a set-up/hold time margin of the signal and reduces a valid window. Reduction in the valid window degrades performance of the chip.
Therefore, there is a need for an interface circuit that provides an output signal such that the amount of time required for transitions to the logic high level and the logic low level are balanced and output without minimized skew.